The present invention relates to synchronous processor circuits in a color receiver and, more specifically, to a synchronous processor circuit for reproducing a synchronizing signal externally provided by a video signal source to a color receiver, and supplying the synchronizing signal to each circuit block in the color receiver.
FIG. 14 is a block diagram showing the structure of a conventional synchronous processor circuit. In FIG. 14, the synchronous processor circuit includes an LPF 1 to which a composite signal 5 is externally provided, and a vertical synchronization separating signal 6 is separated therefrom and outputted; a phase delay part 2 for receiving the composite signal 5 and outputting a plurality of horizontal synchronizing signals 19 to 24 each differently delayed in phase; and a vertical synchronizing signal reproduction circuit 3 for receiving the plurality of horizontal synchronizing signals 19 to 24 each differently delayed in phase and the vertical synchronization separating signal 6 and outputting a vertical synchronizing signal 8. The phase delay part 2 includes first to sixth phase delay circuits 201 to 206. The LPF is a low pass filter. The operation of this synchronous processor circuit is described next below.
FIG. 15 is a time chart which explains the operation of the conventional synchronous processor circuit. In the upper part of the drawing, t1 to t13 indicate time at a regular interval. To be specific, time t1 to time t13 indicate timing for a horizontal synchronizing signal to rise. As shown in FIG. 15, the composite signal 5 externally provided to a display is a synchronizing signal onto which a vertical synchronizing signal and a horizontal synchronizing signal are superimposed.
In FIG. 15, the horizontal synchronizing signal is a pulse signal which rises every time at times t1 to time t13. The vertical synchronizing signal is a pulse signal which rises at time t4 and falls at time t8. Once inputted into the LPF 1, such composite signal 5 is cut off with any horizontal synchronizing frequency component which is high in frequency. Therefore, the LPF 1 is capable of reproducing the vertical synchronization separating signal 6 with any horizontal synchronizing frequency component subtracted from the composite signal 5.
The composite signal 5 is also provided to each of the first to sixth phase delay circuits 201 to 206 in the phase delay part 2. Those inputted composite signals 5 each generate a pulse corresponding to a period of the horizontal synchronizing signal. By using the pulses corresponding to the period of the horizontal synchronizing signal, the first to sixth phase delay circuits 201 to 206 output horizontal synchronizing signals 19 to 24 varied in phase with a predetermined interval in the corresponding phase delay circuit, respectively. The horizontal synchronizing signals 19 to 24 phase-delayed as such and the vertical synchronization separating signal 6 are provided to the vertical synchronizing signal reproduction circuit 3. The vertical synchronizing signal reproduction circuit 3 outputs the vertical synchronizing signal 8 having the phase relationship with the horizontal synchronizing signal determined.
Next, the vertical synchronizing signal reproduction circuit 3 is described for its structure and operation in detail. FIG. 16 is a diagram showing an exemplary detailed structure of the vertical synchronizing signal reproduction circuit 3. In FIG. 16, the vertical synchronizing signal reproduction circuit 3 includes flip-flops 10 to 13, each of which receives the phase-delayed horizontal synchronizing signal 19, 21, 22, or 24 and the vertical synchronization separating signal 6; a NAND gate 15 which receives signals from the flip-flops 10 and 11; a NAND gate 16 which receives signals from the flip-flops 12 and 13; a set-reset flip-flop 17 in which a signal from the NAND gate 15 goes to the set and a signal from the NAND gate 16 to the reset; a multiplexer 18 which receives a signal from the set-reset flip-flop 17 as a control signal and the phase-delayed horizontal synchronizing signals 20 and 23, and outputs a signal 27 which is either one of the horizontal synchronizing signals; and a flip-flop 14 which receives the vertical synchronization separating signal 6 and the output signal 27 from the multiplexer 18, and outputs the vertical synchronizing signal 8.
In FIG. 16, the flip-flop 14 plays a a role as a latch means for latching a vertical synchronization separating signal, and outputting a synchronizing signal having the phase relationship with the horizontal synchronizing signal determined. The multiplexer 18 plays a role as a signal selection means for selecting, for output, a signal for latching the vertical synchronization separating signal from among a plurality of phase-delayed signals. The flip-flops 10 to 13, the NAND gates 15 and 16, and the set-reset flip-flop 17 play a role as signal selection control means for outputting a signal to control the multiplexer 18 which phase-delayed signal is selected therein. The operation of such structured vertical synchronizing signal reproduction circuit 3 is described next below by referring to FIGS. 16 and 17.
FIG. 17 is a time chart showing the operation of the vertical synchronizing signal reproduction circuit 3 from time t4 to time t5 in FIG. 15. In FIG. 17, a timing (denoted by time tA in the drawing) which coincides with a threshold value between a high level and a low level of the vertical synchronization separating signal 6 is observed between timings for the phase-delayed synchronizing signals 19 and 21 to rise. In such case, as shown in FIG. 17, the output signal from the NAND gate 15 changes in level from high to low with the timing when the phase-delayed horizontal synchronizing signal 21 rises. The signal is a set incoming signal 25 which is inputted into the set terminal of the set-reset flip-flop 17.
Further, in FIG. 17, the timing which coincides with the threshold value between the high level and the low level of the vertical synchronization separating signal 6 is not observed between timings for the phase-delayed horizontal synchronizing signals 22 and 24 to rise. Therefore, as shown in FIG. 17, an output signal 26 from the NAND gate 16 remains in the high level. The signal is a reset incoming signal 26 which is inputted into the reset terminal of the set-reset flip-flop 17.
Once such set incoming signal 25 and reset incoming signal 26 are provided to the set-reset flip-flop 17, as shown in FIG. 17, an output signal 33 from the set-reset flip-flop 17 is fixed in the low level. The output signal 33 from the set-reset flip-flop 17 is provided to a control terminal of the multiplexer 18.
When receiving a signal high in level in the control terminal, the multiplexer 18 selects the phase-delayed horizontal synchronizing signal 20 for output. When a signal low in level is inputted thereto, the multiplexer 18 selects the phase-delayed horizontal synchronizing signal 23 for output. Accordingly, the multiplexer 18 having the signal low in level provided to its control terminal selects and outputs the phase-delayed horizontal synchronizing signal 23.
The phase-delayed horizontal synchronizing signal 23 can assuredly be latched with the vertical synchronization separating signal 6 with the timing which coincides with the threshold value between the high level and low level thereof. This is because, as described in the foregoing, the timing which coincides with the threshold value between the high level and the low level of the vertical synchronization separating signal 6 is observed between the timings for the phase-delayed horizontal synchronizing signals 19 and 21 to rise. Therefore, it is not certain whether the phase-delayed horizontal synchronizing signal 20 between the phase-delayed horizontal synchronizing signals 19 and 21 is capable for latching. Accordingly, the flip-flop 14 can assuredly latch the vertical synchronization separating signal 6 with the help of the phase-delayed horizontal synchronizing signal 23.
In the foregoing, by referring to FIG. 17, it has been exemplarily described the case where the timing which coincides with the threshold value between the high level and the low level of the vertical synchronization separating signal 6 is observed between the phase-delayed horizontal synchronizing signals 19 and 21. Herein, the timing which coincides with the threshold value between the high level and the low level of the vertical synchronization separating signal 6 may be observed between the timings for the phase-delayed horizontal synchronizing signals 22 and 24 to rise. In such case, the multiplexer 18 selects, for output, not the phase-delayed horizontal synchronizing signal 23 but the phase-delayed horizontal synchronizing signal 20. Accordingly, similar to the above-described case, the flip-flop 14 can assuredly latch the vertical synchronization separating signal 6.
In such manner, by receiving the phase-delayed horizontal synchronizing signals 19 to 24 from the phase delay part 2 as signals for detecting the timing which coincides with the threshold value between the high level and the low level of the vertical synchronization separating signal 6, the vertical synchronizing signal reproduction circuit 3 can determine the phase relationship between the vertical synchronizing signal and the horizontal synchronization signals. As such, the vertical synchronizing signal reproduction circuit 3 can assuredly latch the vertical synchronization separating signal 6, and thus can supply, to each digital signal processor circuit arranged in the display, the vertical synchronizing signal 8 which has been accurately reproduced.
According to the conventional synchronous processor circuit structured as such, however, a stabilized vertical synchronizing signal cannot be assuredly obtained if, as shown in FIG. 15, the timings which coincide with the threshold value between the high level and the low level of the vertical synchronization separating signal 6 separated and reproduced by the LPF 1 approximately coincide with both pulse timings of the phase-delayed horizontal synchronizing signals 20 and 23. This is because the phase relationship between the vertical synchronization separating signal 6 and the horizontal synchronizing signal is not determined.
FIG. 18 are diagrams schematically showing a partially-enlarged waveform of the vertical synchronization separating signal 6. A dotted line laterally drawn in the drawings indicates the threshold value between the high level and the low level of the vertical synchronization separating signal 6. To be specific, the threshold value is used by the flip-flops 10 to 14 which receive the vertical synchronization separating signal 6 to distinguish the level thereof between high and low.
FIG. 18(a) is the diagram schematically showing the waveform at a front part of the vertical synchronization separating signal 6 in the range between time t4 and time t5 in FIG. 11. In the drawing, tA indicates a time when the vertical synchronization separating signal 6 reaches the threshold value as in FIG. 17. In the drawing, Ts indicates a period between time t4 and time tA. FIG. 18(b) is the diagram schematically showing the waveform at a rear part of the vertical synchronization separating signal 6 in the range between time t8 and time t9 in FIG. 11. In the drawing, tB indicates a time when the vertical synchronization separating signal 6 reaches the threshold value. In the drawing, Te indicates a period between time t8 and time tB.
As shown in FIG. 18, the waveform of the vertical synchronization separating signal 6 often differs in shape between the front part and the rear part, and the timings tA and tB which coincide with the threshold value between the high level and the low level of the vertical synchronization separating signal 6 often differ between the front part and the rear part thereof. Therefore, at the rear part of the vertical synchronization separating signal 6, unlike the above-described case in FIG. 17, the timing which coincides with the threshold value between the high level and the low level of the vertical synchronization separating signal 6 may be observed between the timings for the phase-delayed horizontal synchronizing signals 22 and 24 to rise. If this is the case, the multiplexer 18 may select, for output, the phase-delayed horizontal synchronizing signal 20, or the phase-delayed horizontal synchronizing signal 23. Consequently, the output signal 27 from the multiplexer 18 fails to be constant in horizontal synchronizing frequency as shown in FIG. 15. As such, according to the conventional structure, the phase relationship between the vertical synchronization separating signal 6 and the horizontal synchronizing signal is not determined. Therefore, the vertical synchronization signal provided therefrom cannot be stabilized enough.
Further, in such a case as shown in FIG. 15, as to the vertical synchronizing signal provided by the vertical synchronizing signal reproduction circuit 3, a pulse width thereof does not become integral multiple of the horizontal synchronizing signal. Consequently, the synchronous processor circuit in the display becomes complicated in structure, thereby rendering the cost increased.
Especially, such phenomenon often occurs in a multiscan monitor, which receives incoming signals varied in scanning frequency from a video signal source. Generally, the LPF 1 is fixed in cutoff frequency. Therefore, the cutoff frequency of the LPF 1 may be too heavy (to low) for the vertical synchronizing signal component superimposed on the composite signal 5 depending on its pulse width. If this is the case, the vertical synchronization separating signal 6 provided by the LPF1 may get very blunt. As exemplarily shown in FIG. 18, the vertical synchronization separating signal 6 provided by the LPF1 shows a gradual change from time t8 to time t9, or from time t4 and time t5. As a result, as described in the foregoing, the timings which coincide with the threshold value between the high level and the low level of the vertical synchronization separating signal 6 approximately coincide with both pulse timings of the above-described phase-delayed horizontal synchronizing signals 20 and 23, thereby causing such problem as above-described.
Therefore, an object of the present invention is to provide a synchronous process circuit capable of improving a display""s synchronization stability by determining a phase relationship between a vertical synchronizing signal and horizontal synchronizing signals, and a circuitry structure of which can be simplified by setting a pulse width of the vertical synchronizing signal to be the integral multiple of the horizontal synchronizing signal.
A first aspect of the present invention is directed to a synchronous processor circuit arranged in a display for reproducing a synchronizing signal from a composite signal provided by a video signal source for stabilizing synchronization in the display, the circuit comprising:
a low pass filter for outputting a vertical synchronization separating signal by separating a vertical synchronizing signal from the composite signal;
a frequency divider circuit for outputting a vertical phase detection signal obtained by frequency-dividing the vertical synchronization separating signal into 1/n (where n is multiple of 2);
a plurality of phase delay circuits for outputting phase-delayed signals each differently delayed in phase with respect to a horizontal synchronizing signal included in the composite signal; and
a vertical synchronizing signal reproduction circuit for outputting the synchronizing signal having a phase relationship with the horizontal synchronizing signal determined by receiving the vertical synchronization separating signal, the vertical phase detection signal, and the plurality of phase-delayed signals.
As described above, in the first aspect of the present invention, it becomes possible to determine the phase relationship between the vertical synchronizing signal and the horizontal synchronizing signal. Accordingly, the stabilized vertical synchronizing signal can be supplied to each circuit arranged in the display.
According to a second aspect of the present invention, in the first aspect of the present invention,
the frequency divider circuit outputs the vertical phase detection signal obtained by dividing the vertical synchronizing signal into xc2xd.
As described above, in the second aspect of the present invention, it becomes possible to swiftly respond to any minute change in phase of the incoming composite signal by having the xc2xd frequency divider circuit provided. Accordingly, the stabilized vertical synchronizing signal can be supplied to each circuit arranged in the display.
According to a third aspect of the present invention, in the first aspect of the present invention,
the vertical synchronizing signal reproduction circuit comprises:
latch means for latching the vertical synchronization separating signal, and outputting the synchronizing signal having the phase relationship with the horizontal synchronizing signal determined;
signal selection means for selecting a signal to be used by the latch means to latch the vertical synchronization separating signal from among the plurality of phase-delayed signals for output to the latch means; and
signal selection control means for receiving the vertical phase detection signal and the plurality of phase-delayed signals, and outputting, to the signal selection means, a signal for controlling the signal selection control means which of the phase-delayed signals is selected therein.
As described above, according to the third aspect of the present invention, the phase relationship between the vertical synchronizing signal and the horizontal synchronizing signal can be determined with the help of a plurality of phase-delayed signals inputted as signals for detecting a timing which coincides with the threshold value between the high level and the low level of the vertical synchronization separating signal.
According to a fourth aspect of the present invention, in the first aspect of the present invention,
the synchronous processor circuit further comprises a pulse width reproduction circuit for receiving the signal from the vertical synchronizing signal reproduction circuit, and reproducing the synchronizing signal having a predetermined pulse width.
As described above, according to the fourth aspect of the present invention, as long as the reference timing is stabilized, regardless of the other timing""s stability, the stabilized vertical synchronizing signal can be outputted with the counting operation carried out according to the set pulse width.
According to a fifth aspect of the present invention, in the fourth aspect of the present invention,
the pulse width reproduction circuit comprises:
a counter, in which a counter value is set to 0 when the signal provided by the vertical synchronizing signal reproduction circuit rises, for incrementing the counter value according to an incoming clock signal; and
a comparator for comparing pulse width setting data provided to set the pulse width and the counter value, and outputting a signal whose pulse width is based on the pulse width setting data.
As described above, in the fifth aspect of the present invention, the pulse width reproduction circuit can output the stabilized signal according to the pulse width which is previously set or calculated by operation.
A sixth aspect of the present invention is directed to a synchronous processor circuit arranged in a display for reproducing a synchronizing signal from a composite signal provided by a video signal source for stabilizing synchronization in the display, the circuit comprising:
a low pass filter for outputting a vertical synchronization separating signal by separating a vertical synchronizing signal from the composite signal;
a plurality of phase delay circuits for outputting phase-delayed signals each differently delayed in phase with respect to a horizontal synchronizing signal included in the composite signal; and
a vertical synchronizing signal reproduction circuit for outputting a signal having the phase relationship with the horizontal synchronizing signal determined by receiving the vertical synchronization separating signal, and the plurality of phase-delayed signals; and
a flip-flop for latching the signal provided by the vertical synchronizing signal reproduction circuit, and outputting the synchronizing signal whose period is an integral multiple of the horizontal synchronizing signal.
As described above, in the sixth aspect of the present invention, it is possible to obtain the vertical synchronizing signal having the pulse width of the integral multiple of the horizontal synchronizing signal with a structurally simplified circuit. Accordingly, the synchronous processor circuit in the display can be simplified in structure.
According to a seventh aspect of the present invention, in the sixth aspect of the present invention,
the vertical synchronizing signal reproduction circuit comprises:
latch means for latching, and outputting the synchronizing signal having the phase relationship with the horizontal synchronizing signal determined;
signal selection means for selecting a signal to be used by the latch means to latch the vertical synchronization separating signal from among the plurality of phase-delayed signals for output to the latch means; and
signal selection control means for receiving the vertical phase detection signal and the plurality of phase-delayed signals, and outputting, to the signal selection means, a signal for controlling the signal selection control means which of the phase-delayed signals is selected therein.
As described above, in the seventh aspect of the present invention, the phase relationship between the vertical synchronizing signal and the horizontal synchronizing signal can be determined with the help of a plurality of phase-delayed signals inputted as signals for detecting a timing which coincides with the threshold value between the high level and the low level of the vertical synchronization separating signal.
According to an eighth aspect of the present invention, in the sixth aspect of the present invention,
the synchronous processor circuit further comprises a pulse width reproduction circuit for receiving the signal from the flip-flop, and reproducing the synchronizing signal having a predetermined pulse width.
As described above, in the eighth aspect of the present invention, as long as the reference timing is stabilized, regardless of the other timing""s stability, the stabilized vertical synchronizing signal can be outputted with the counting operation carried out according to the set pulse width. Therefore, with a structurally simplified circuit, even with respect to the interlace signal, the vertical synchronizing signal can have the pulse width of the integral multiple of the horizontal synchronizing signal. Therefore, it becomes possible to simplify the synchronous processor circuit in the display.
According to a ninth aspect of the present invention, in the eighth aspect of the present invention,
the pulse width reproduction circuit comprises:
a counter, in which a counter value is set to 0 when the signal provided by the flip-flop rises, for incrementing the counter value according to an incoming clock signal; and
a comparator for comparing pulse width setting data provided to set the pulse width and the counter value, and outputting a signal whose pulse width is based on the pulse width setting data.
As described above, in the ninth aspect of the present invention, the pulse width reproduction circuit can output the stabilized signal according to the pulse width which is previously set or calculated by operation.